Digital Verification Engineer: Telegent Systems

Job Title: Engineer, Digital Verification

Location: Sunnyvale , CA

Telegent has delivered a breakthrough technology that has transformed the landscape of the mobile TV industry, by enabling phones to receive TV broadcasts from both analog and digital broadcast standards. Telegent's support for analog standards is unique in the industry, enabling manufacturers to provide consumers with worldwide access to free, live TV programming using existing broadcast infrastructure that has been built out over the last sixty years. This capability has led to shipments that have now surpassed those of all other digital subscription standards combined, resulting in millions of mobile TV viewers in Asia, Latin America, the Middle East, Europe and Africa .

Responsibilities:

· Develop verification environment and methodology

· Create test plans for both block-level and chip-level environments

· Design and implement design verification environments

· Generate tests and debug the Verilog design

Requirements:

• Capable of verifying large, DSP centric designs.
• Capable of verifying designs with embedded CPU's and sizeable firmware and host side software.
• Has worked with at least one design in excess of one million placeable instances.
• Must be strong in Object-Oriented Programming.
• Must have experience with Verilog, System Verilog (or Vera), and C.
• Willingness to work in small teams (possibly as small as one) and willingness to contribute in all aspects of the design cycle if and when necessary.
• Willingness to gather and iteratively improve code coverage.
• Experienced with gate level, annotated simulation environments.
• BSEE or MSEE (preferred) + 3-8 years experience

Desired:

• Experience with OVM or VMM is a plus.
• Experience with Cadence tools preferred.
• Knowledge in DSP algorithm preferred, NTSC, DVB-T, MPEG.
• Strong Perl skills is a plus.